1. Field of Invention
The present invention relates to a method for fabricating semiconductor devices and, more particularly, to a lithography method for suppressing scum in an exposure process.
2. Related Technology
As integrated circuit devices such as semiconductor devices become more highly integrated, many studies on improving electrical characteristics of the device or securing process margins have been carried out. In the case of semiconductor memory devices such as a NAND flash memory or a DRAM memory, memory capacities have become larger and critical dimensions (CD) of patterns constituting the device have rapidly decreased in size. It has become more important to transfer circuit pattern layouts designed for the devices on wafers in lithography processes.
As pattern sizes of semiconductor devices become smaller and semiconductor devices having new structures are developed, resolution enhancement technologies are frequently used in exposure processes. For one of the resolution enhancement technologies, asymmetric illumination systems, such as dipole illumination systems, have been introduced in exposure processes. In cases of introducing dipole illumination systems, there is merit in forming circuits having relatively minute lines and spaces. Scum, which is undesired photoresist residue, may be formed around larger patterns or pad patterns that are designed to have a relatively large size and space as compared to line patterns.
FIGS. 1 to 3 illustrate scum formed in an exposure process. Referring to FIG. 1, a dipole illumination system 10 to improve the resolution of a line pattern and a space pattern can be introduced by using an aperture structure having openings 11 in an x-direction of an x-y coordinate system, as illustrated. As positions of the openings 11 are closer to edges and farther from the center of the aperture structure, a more extremely modified dipole illumination system can be implemented. In the case of using the extreme dipole illumination system illustrated in FIG. 1 with a high number of aperture (NA) lens system of 0.90 NA, an image of a line and space pattern having a more minute line width can be implemented on a wafer.
When implementing a pattern having a more minute line width by using such an extreme illumination system, scum can be formed around larger patterns. As shown in FIG. 2, an original layout 20 of a circuit pattern for a semiconductor device is designed by setting both line patterns 21 for wiring, and spaces between the line patterns, as reference patterns. A large pattern, such as a pad 23 for an interconnection wiring, having a relatively large line width as compared to a line pattern 21, is also needed to implement a circuit. A space 25 between pads 23 is also set with a relatively large interval, compared to another space 26 between line patterns 21.
Accordingly, in the case of projecting an original layout 20 of such a circuit pattern on a photoresist of a wafer by using the extreme dipole illumination system as shown in FIG. 1, a layout 30 of a photoresist pattern can be implemented as shown in FIG. 3. Along with the shape of a line pattern 31 and pads 33, scum 37 comprising undesired photoresist residue can be defectively generated in a space 35 between the pads. The region where the scum 37 is generated can be understood as a region where insufficient light energy is exposed. As interference of exposure light occurs depending on the pads 23 in FIG. 2 positioned around the region where the scum 37 is generated and the space 35 therebetween, the scum 37 results.
Since the scum 37 of the photoresist causes undesired pattern formation on a wafer, a technology of suppressing or preventing the scum 37 in order to suppress a defective pattern on a wafer is desirable. In order to prevent the scum 37, various optical proximity correction technologies or resolution improvement technologies may be tried.